发明名称 BUFFER UNIT AND SWITCHING UNIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a buffer unit and a switching unit that can avoid frame- interleaving and reduce that amount of hardware units. SOLUTION: The buffer unit and the switching unit are provided with fixed length packet storage means 28-1 to 28-m, that store a fixed length packet to each output path; a multi-cast processing means 29 that stores a multi-cast packet having destinations and that transfers the multi-cast packets to the fixed length packet storage means 28-1 to 28-m depending on the destination; and a control means 25 that monitors the storage state of the fixed length packet storage means 28-1 to 28-m and, that controls to transfer the multi-cast packets in-between variable length packets consisting of the fixed length packets, so that the task above is resolved.</p>
申请公布号 JP2002033749(A) 申请公布日期 2002.01.31
申请号 JP20000217604 申请日期 2000.07.18
申请人 FUJITSU LTD 发明人 MATSUOKA NAOKI;TOMONAGA HIROSHI;KAWARAI KENICHI
分类号 H04L12/56;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04L12/56
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