SEMICONDUCTOR STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To solve the problems that correct data can not be read because a bit line is selected before a column address is fetched forward and a sense amplifier amplifies the data of the bit line when the input cycle of a read command that is inputted, e.g. after two cycles after an operation start command is inputted is made fast and also that correct data can not be written because the bit line is selected before correct write data are inputted to a write circuit when the input cycle of a write command is made fast in the conventional double data rate synchronous DRAM. SOLUTION: In a clock synchronous type memory such as a double data rate synchronous DRAM, a register capable of setting a value (forward latency) at which the input cycle of a read or write command is designated is provided and registers (124 and 125) for timing adjustment for delaying as much as a prescribed cycle period in accordance with the forward latency set in the register are provided on the signal path of a column address system between a column address latch circuit (110) and a column decoder (116).