Data I/O buffer control circuit

摘要

A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).