| 摘要 |
PROBLEM TO BE SOLVED: To provide a parallel signal processing unit that can extend the shortest part of a setup margin as a time required, when assembling parallel data into serial data and avoid the power consumption time from being concentrated at a single point. SOLUTION: A 1 to n serial parallel conversion circuit 113 synchronously receives n-multiple data 111 with a system clock 112 and separates the data 111 into 1st-n-th separated data 1141-114n. They are given to 1st-n-th processing sections 1171-117n with different timings by 1st-n-th 1/n clock signals 1151-115n and processed, and an n to 1 parallel serial conversion circuit 119 at the post stage assembles the data in respective timings to obtain an n-multiple data 121. Thus, the setup margin of the data of each system in the n to 1 parallel serial conversion circuit 119 is made constant. Furthermore, since the processing timing differs from each system, the power consumption time can be distributed. |
