| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the clock drift in the doubled clock device and the same caused when switching a receiving clock, and to improve reliability required in a communication system. SOLUTION: In the doubled clock device, there is compared the phase of the receiving clock inputted from each upper clock feeding device with the phase of the clock outputted from an own line device, then the phase difference resulting from the comparison, is quantized. The quantized data is shared in the own line device and the other line device, smoothing is performed with digital PLL in each own line device, based on the quantized data. An operative line device and an alternative line device are operated, based on the same quantized data, thus the clock drift caused when switching the device, is reduced. Further, by the control with digital PLL based on the shared quantized data, the output clock drift is reduced to the transient input clock drift including the switching of the receiving clock.</p> |
