| 摘要 |
A nonvolatile memory cell utilizing planar control gates, which provides advantages of being compatible with self-aligned silicide processes and providing a planar surface for subsequent wiring processes. A substrate defines a first NVRAM region having large floating gate areas with smaller areas cutout to isolate individual memory cells, and a second CMOS Logic region. ONO is deposited on the floating gate areas, and a thick poly layer is deposited in a blanket manner over the first and second regions of the substrate. Resist shapes are patterned over the logic areas in the array where necessary according to a predetermined density algorithm. The poly layer is reactive ion etched, followed by a chemical mechanical polishing (CMP) operation. The final poly gate thickness is 200-220 nm in the CMOS logic areas and in the NVRAM control gate areas between floating gate regions, but only 100-120 nm for the NVRAM control gates over the floating gates. The control gate physical thickness is decoupled (isolated) from the standard logic by standard photoetching processes, and the final structure appears identical from a topological perspective to a standard CMOS structure.
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