| 摘要 |
A memory system for use in a high-speed computer system, such as a super computer, has synchronous-type storage elements organized in groups for storing data. A storage control section has a clock generator circuit that generates parallel transfer clock signals that compensate for overall transfer delay when data is transferred to the storage elements. Each of the storage elements groups has a phase-locked locked loop circuit that outputs timing signals for accepting data, including address and control signals, etc., at the storage elements. Data is read out from the storage elements to a return data holding circuit of the storage control section using return parallel transfer clock signals, which are controlled by a control section phase-locked loop circuit that receives as an input a timing output of the phase-locked loop circuit of one of the storage element groups. A clock distribution circuit controls the supply of clock signals to a flip-flop group in the return data holding circuit. A timing signal supplied to one of the flip-flop circuits is returned to the storage control phase-locked loop circuit for controlling the timing of the acceptance of the transferred data in the flip-flop group of the return data holding circuit.
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