Delay locked loop circuit capable of adjusting phase of clock with high precision

摘要

A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second inverters are configured of inverters of different sizes. A phase comparator compares a delay clock's phase with a reference clock's phase and a result of the phase comparison is referred to to count addresses which are in turn used to selectively drive the inverters configuring the first and second inverter circuits, to allow the fine delay circuit to output a signal having a phase between signals having therebetween a phase difference of a fixed amount. Thus the clock's phase can be adjusted with high precision.