发明名称 |
Decoder and reproducing unit |
摘要 |
A slow decode control part divides a reference clock generated by a VCXO at a ratio of a slow speed to a normal speed. An STC circuit counts the divided clock. A time for starting decoding by an MPEG video decode part is decided by comparing a DTS included in MPEG data with the count of the STC circuit. A display time determination part determines a timing for outputting decoded data by comparing a PTS included in the MPEG data with the count of the STC circuit. Decoded data temporarily held in a frame buffer is output in response to a signal generated in a determination part on the basis of frame frequency information included in the MPEG data. Thus, slow reproduction is implemented with a high degree of freedom not limited to an integer-fractional speed without requiring a complicated circuit structure.
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申请公布号 |
US2001055469(A1) |
申请公布日期 |
2001.12.27 |
申请号 |
US20000725289 |
申请日期 |
2000.11.29 |
申请人 |
SHIDA TETSURO;KOSAKA HIDEAKI |
发明人 |
SHIDA TETSURO;KOSAKA HIDEAKI |
分类号 |
G11B15/087;G11B15/18;G11B20/14;G11B27/00;H04N5/783;H04N5/92;H04N5/93;H04N5/937;H04N7/32;H04N7/46;H04N7/50;H04N9/804;(IPC1-7):H04N5/783;H04N5/91;H04N7/26 |
主分类号 |
G11B15/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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