| 摘要 |
PROBLEM TO BE SOLVED: To meet the requirement of jitter tolerance in wide range during a clock recovery action in a clock regenerator. SOLUTION: This disclosed clock regenerator is equipped with a VCO7 which generates a clock signal, a phase comparator 1 which generates a first control signal by comparing the phases of an input data signal and a clock signal, a phase/frequency comparator 2 which generates a second control signal by comparing the phases of a divided clock signal and a reference clock signal with each other, a mode switching selector 5 which selects the first control signal or the second control signal, an analog frequency synchronization - IN detecting circuit 9 which detects the phase difference between the divided clock signal and the reference clock signal getting in a predetermined range, and a digital frequency synchronization - OUT detecting circuit 11 which detects the phase difference between the divided clock signal and the reference clock signal getting out of the predetermined range. |
