发明名称 |
Testable integrated circuit, integrated circuit design-for-testability method, and computer-readable medium storing a program for implementing the design-for-testability method |
摘要 |
Apparatus for testing integrated circuits containing a controller or other sequential circuit at actual operating speed while minimizing the length of the test sequence and achieving high fault coverage are provided. The states of a state register are assumed controllable and observable, and a set of test patterns is obtained for a combinational circuit not containing said state register. An invalid-state generation logic circuit is added for generating invalid states, which are states contained in the generated test patterns but cannot be set by a normal transition from the reset state. A multiplexer is added for selecting the output of a next-state generation logic circuit or the invalid-state generation logic circuit for input to the state register based on a state transition mode selection signal. Signals corresponding to pseudo-primary outputs during test generation are made observable, and the multiplexer output signal is externally detectable as a state output signal.
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申请公布号 |
US6334200(B1) |
申请公布日期 |
2001.12.25 |
申请号 |
US19980203372 |
申请日期 |
1998.12.02 |
申请人 |
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER |
发明人 |
FUJIWARA HIDEO;MASUZAWA TOSHIMITSU;OHTAKE SATOSHI |
分类号 |
G01R31/28;G01R31/3183;G01R31/3185;G06F17/50;(IPC1-7):G01R31/28;G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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