发明名称 SCHEDULING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a scheduling circuit that eliminates a cell loss caused in a conventional scheduling circuit to the utmost and can transfer an IP packet with high reliability. SOLUTION: The scheduling circuit consists of an IP scheduling section/ format conversion section 11 that includes a packet FIFO 111, conducts IP scheduling of a received IP packet and converts the IP packet into an ATM cell, cell FIFO sets 12 connected to an output of the section 11, and an ATM scheduling section 13 that applies ATM scheduling to an output in the unit of cells outputted from the cell FIFO sets 12.</p>
申请公布号 JP2001339398(A) 申请公布日期 2001.12.07
申请号 JP20000154718 申请日期 2000.05.25
申请人 NEC CORP 发明人 SAITO TAKASHI
分类号 H04J3/26;H04L12/66;H04L12/813;H04L12/815;H04L12/823;H04L12/851;H04L12/863;H04L12/927;H04L29/06;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04J3/26
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