| 摘要 |
A semiconductor memory device having a reduced circuit area. The semiconductor memory device includes a memory cell array connected to an address decoder, a sense amplifier, a write amplifier, and a command decoder. A first serial/parallel converter is adjacent to the address decoder. A parallel/serial converter is adjacent to the sense amplifier. A second serial/parallel converter is adjacent to the write amplifier. A third serial/parallel converter is adjacent to the command decoder. The serial/parallel converters and the parallel/serial converter are each connected to an input/output circuit via a pair of wires.
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