Termination circuits and methods therefor

摘要

An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor. The circuit also includes a top ESD protection transistor having a second node coupled to a second potential and a top ESD protection transistor intrinsic diode reverse biasedly coupling the node to a second reference voltage supply and a top threshold reference transistor coupled to the second reference voltage supply. The top threshold reference transistor provides a second bias voltage to the top ESD protection transistor gate that biases the top clamping transistor gate at about a second threshold voltage below the second reference voltage that represents a threshold voltage of said top ESD protection transistor.