发明名称 Process for passivating top interface of damascene-type Cu interconnect lines
摘要 The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized metallization patterns, e.g., of copper, in-laid in the exposed upper surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, exposed upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form passivated top interfaces. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in "back-end" metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
申请公布号 US6319819(B1) 申请公布日期 2001.11.20
申请号 US20000484439 申请日期 2000.01.18
申请人 ADVANCED MICRO DEVICES, INC. 发明人 BESSER PAUL R.;ERB DARRELL M.
分类号 H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/768
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