| 摘要 |
A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input coupled to an overlap_en signal, a second input coupled to an inverted overlap_en signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal. Each clock inverter leg can further include an asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit and an input coupled to a waitr_signal that can be used to delay and adjust breadth of non-overlap. Each leg can further include a tri-state inverter circuit having a first input coupled to an output of the AVD circuit, and a second input coupled to the inverted first clock input signal. Each leg can further include an inverter having an input coupled to an output of the tri-state inverter circuit, and an output coupled to a first clock output signal. |
