| 摘要 |
The purpose of the present invention is to provide a semiconductor memory device which is capable of suppressing an increase in chip surface area and in power consumption resulting from peripheral circuitry even when the capacity thereof becomes large, and which, moreover, does not experience discrepancies in clock skew and the like between I/Os, and which is capable of high speed operation. 4-bit parallel data comprising a 0th through 3rd bit are exchanged simultaneously between memory cell arrays with respect to each I/O pin in DQ0-DQ7. Data of the 0th bit through 3rd bit are inputted and outputted with the exterior in that order via input/output interface circuit 5-1. At data load signal LOAD, flip flop groups 12-0 through 12-3 incorporate the 0th through 3rd bit data corresponding to 8 I/O pins. It is necessary to initially read out the 0th bit parallel data to the exterior, so that flip flop group 12-0 is disposed in closest proximity to the input/output interface circuit 5-1. The 8 bits are shifted together from flip flop group 12-3 to flip flop group 12-0 synchronously with clock signal CLOCK, and the 0th through 3rd bit data are outputted.
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