Circuit, structure and method of testing a semiconductor, such as an integrated circuit

摘要

A method of testing an integrated circuit having a layout structure which includes a plurality of branch structures, the method comprising the steps of: (A) generating a control current in response to an input reference; (B) establishing a respective branch current through each of the plurality of branch structures when a process bias supports fabrication of a respective predetermined dimension associated with the branch structures; and (C) generating, in response to the branch currents, an output indicative of the process bias obtained during fabrication of the layout structure.