| 摘要 |
The present invention provides an improved, efficient DLL design. In one embodiment, it includes a voltage controlled delay line, a phase comparator, and a dynamic bias source. The delay line has an associated delay that is controllably adjusted by a received control signal. The delay line also has an input for receiving a reference signal and one or more outputs for providing one or more delayed versions of the reference signal. The phase comparator is operably connected to the delay line in a closed loop fashion for controlling the control signal based on the phase difference between the reference signal and one of the one or more delayed reference signal versions to cause the delay line to generate an output delayed reference signal that is in synch. with the reference signal but delayed from it by a predetermined quantity. The dynamic bias source provides power to the delay line as it is needed so that the control signal is not adversely affected by changes in the delay lines power demands.
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