发明名称 VERTICAL DRAM DEVICE PROVIDED WITH CHANNEL ACCESS TRANSISTOR AND STACKED TYPE STORAGE CAPACITOR
摘要 PROBLEM TO BE SOLVED: To provide a comparatively high density integrated circuit memory device that keeps enough electrostatic capacity level for suitable device operation. SOLUTION: The integrated circuit memory device contains a substrate 22 having at least one connecting line 23 internally, and the multiple memory cells 20 formed on the substrate 22. Each of the memory cells 20 contains a pillar 40 which is composed of a lower source/drain region 42 for a cell access transistor electrically connected to the connecting line 23, an upper source/drain region 44 for the cell access transistor, and at least one channel region 46 extending in the vertical direction between the lower source/drain region 42 and the upper source/drain region 44. And moreover, each of the memory cells 20 contains at least one lower dielectric layer adjoining in the vertical direction with the substrate 22 and adjoining in the horizontal direction with the pillar 40, and at least one upper dielectric layer arranged in the vertical direction and with a space at the upper part of at least one lower dielectric layer and adjoining in the horizontal direction with the pillar 40.
申请公布号 JP2001308203(A) 申请公布日期 2001.11.02
申请号 JP20010122417 申请日期 2001.04.20
申请人 AGERE SYSTEMS GUARDIAN CORP 发明人 CHOI SEUNGMOO
分类号 H01L21/8242;H01L27/108 主分类号 H01L21/8242
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