| 摘要 |
A system and method are disclosed for synchronizing a predetermined repeated data sequence contained in a first data signal at a first sample rate with the same predetermined repeated data sequence contained in a second data signal at a second sample rate in a data communications device. The system preferably includes a digital signal processor operating pursuant to logic stored on a memory. The logic includes synchronization logic which reduces the first sample rate to a predetermined correlation sample rate using a first decimator, resulting in a first reduced data signal. The synchronization logic also reduces the second sample rate to the same predetermined correlation sample rate using a second decimator, resulting in a second reduced data signal. Finally, the synchronization logic determines a sequence offset between the predetermined repeated data sequence contained in the first reduced data signal and the predetermined repeated data sequence contained in the second reduced data signal using a correlator. This sequence offset is used to determine a time delay that is applied to the second data signal, thereby synchronizing the predetermined repeated data sequence contained in the first and second data sequences.
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