TWO CLOCK DOMAIN PULSE TO PULSE SYNCHRONIZER

摘要

A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms of frequency and/or phase is constituted by a transmitting section functioning with the first clock (CLK1), a receiving section functioning with the second clock (CLK2) and a feedback section functioning with the first clock (CLK1). A bidirectional synchronizer transfers commands with a strobe signal (STR) from a microprocessor interface (MPRI) functioning with the first clock (CLK1) to an application circuit (APL) functioning with the second clock (CLK2) and alarm signals from the application circuit (APL) to the microprocessor interface (MPRI).