发明名称 |
Memory cell configuration for a 1T/1C ferroelectric memory |
摘要 |
A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.
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申请公布号 |
US2001033510(A1) |
申请公布日期 |
2001.10.25 |
申请号 |
US20010764223 |
申请日期 |
2001.01.16 |
申请人 |
ALLEN JUDITH E.;LEHMAN LARK;WILSON DENNIS R. |
发明人 |
ALLEN JUDITH E.;LEHMAN LARK;WILSON DENNIS R. |
分类号 |
G11C11/22;(IPC1-7):G11C11/22 |
主分类号 |
G11C11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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