| 摘要 |
<p>A logic circuit for generating a control voltage includes a ramp DAC and a main DAC. When the control voltage is needed, such as when an associated crystal oscillator is being 'turned on', an input reference voltage is supplied to both the ramp DAC and the main DAC. The ramp DAC generates an output based on the input reference voltage and L supplied control bits for a (preferably short) ramp time period. The output from the ramp DAC is fed to a filter circuit that includes a capacitor to charge the capacitor and the control voltage is generated at least in part from the ramp DAC output as filtered by the capacitor. When the ramp period ends, the state of the input reference voltage is changed and the output from the main DAC, based on the changed input reference voltage and N control bits, is input to the filter. Such a two DAC arrangement allows for a shorter time constant circuit to be employed in association with the ramp DAC and a longer time constant circuit to be employed in association with the main DAC, allowing for quick ramp up of the control voltage. By adjusting the input reference voltage when supplied to the ramp DAC during the ramp period, as compared with when supplied to the main DAC after the ramp period, the circuit allows emulation of greater than L-bit control for the ramp DAC. Thus, the output of the ramp DAC may be more closely 'tuned' to the output of the main DAC without increasing the number of control bits supplied to the ramp DAC.</p> |
