Semiconductor memory device with write driver reset function

摘要

In a DRAM's timing generator with a write-state signal generation circuit responding to activation of a write enable signal to activate a write-state signal and a write driver enable signal generation circuit responding to activation of the write-state signal to activate a write driver enable signal, there is provided a driver reset circuit responding to inactivation of a write enable signal to activate a driver reset signal applied to an NAND circuit downstream of a flip-flop circuit provided in a write driver enable signal generation circuit.