Apparatus of reducing power consumption of single-ended SRAM

摘要

An apparatus of reducing power consumption of a single-ended Static Random Access Memory (hereinafter referred as SRAM) is provided. The apparatus consists of at least an extra column of status memory cell and a majority detector by which a bit status of a written data is detected and by which the value of the bit status is written into the extra column of status memory cell. The apparatus further includes a data scrambler by which the written data is converted into a storage data with a minority of 0 bits based on the value of bit status and by which the storage data is written into the main single-ended SRAM cell. The apparatus further includes a data de-scrambler by which the storage data in the main single-ended SRAM cell is converted into its original format based on the value of bit status stored in the extra column of memory cell and by which the data in its original format is output. Since the data stored in the main single-ended SRAM cell has a majority of 1 bits, the apparatus can reduce the power consumption of the single-ended SRAM.