BIP-N ARITHMETIC UNIT, AND BIP-N ARITHMETIC SYSTEM USED THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a BIP-N arithmetic unit that can apply a BIP-N arithmetic operation to a concatenation signal with a simple configuration and has the configuration providing ease of extension depending on the kind of a concatenation signal. SOLUTION: A serial parallel conversion circuit 1 applies byte interleave demultiplexing to a received STS-3c concatenation signal, serial parallel conversion circuits 2-4 apply bit interleave demultiplexing to the demultiplexed concatenation signals, and BIP-N arithmetic circuits 5-7 conduct an arithmetic operation of a BIP-N code. Flip-flop circuits 8-10 latch the outputs of the circuits 5-7 and output them to EX-OR gates 11-13. The EX-OR gates 11-13 and concatenation control circuits 14-16 are connected in a chain so as to apply a chaining arithmetic operation to the arithmetic results of the BIP-N arithmetic circuits 5-7 and an output of the EX-OR gate 11 is outputted as a BIP-N arithmetic result.