发明名称 |
Data output buffer with precharge |
摘要 |
A data output buffer includes an output node, and a first stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state. A second stage is connected to the first stage and to the output buffer. The first and second stages are responsive to a second control signal for enabling output of new data. A precharge logic circuit precharges the output node to the intermediate voltage as a function of data last output, and as a function of first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.
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申请公布号 |
US6292405(B1) |
申请公布日期 |
2001.09.18 |
申请号 |
US20000636363 |
申请日期 |
2000.08.11 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
NICOSIA SALVATORE;PAGANO GIOVANNI;DE AMBROGGI LUCA GIUSEPPE;PALUMBO GAETANO |
分类号 |
G11C7/10;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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主权项 |
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地址 |
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