| 摘要 |
PROBLEM TO BE SOLVED: To provide an SPDIF receiving circuit for realizing the transmission rate determining operation of an SPDIF reception signal and the correct detecting operation of data bits in a small-scaled circuit constitution. SOLUTION: Bit extraction pulse columns pa and pb in a prescribed timing, corresponding to a clock Ck are generated based on the data changing point of an SPDIF signal Si by a pulse column generating circuit 23, and the number of bit data of the SPDIF signal is counted by a B counter 27, and preamble is detected from the SPDIF signal, based on the bit extraction pulse columns pa and pb by a preamble detecting circuit 25. A preamble detection signal Dpa is decoded, and the count value and the phase of the count timing of the B counter 27 is corrected. Then, a lock state is determined uner a condition that the generation of the preamble detection signal Dpa, at prescribed value counting of the B counter is set at least as locked state, and a first lock status signal S1 is outputted. |
