| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an interface circuit for automatically adjusting fluctuations of the delay time of data transmission, and for ensuring phase difference for correctly receiving data. SOLUTION: A logical circuit 101 transmits data inputted from another logical circuit 103 via wiring DATA 107 to a logical circuit 102 and transmits a system clock SCK via wiring DCK 115 to the logical circuit 102. The logical circuit 102 delays the signal C5 transmitted through the DCK by a distributing circuit 117 only by almost the half of the cycle of the SCK, and inputs it as a signal C6 to an FF 109, and sets data D3 at the FF 109 synchronously with the C6. An output D4 of the FF 109 is delayed by a cartable delay circuit 120, and an output D5 is set at an FF 110 in synchronism with the SCK, and an output D6 is outputted to another logical circuit 111. A phase comparator circuit 118 makes phase comparison of the signal C5 with the SCK, and the delay quaintly of the variable delay circuit 120 is controlled by the output 119.</p> |
