| 摘要 |
<p>A domino logic circuit and circuit family is disclosed that has reduced the capacitance on the evaluation node for increased performance. The domino logic circuit preferably includes an inverter, a pre-charge transistor, a logic block, and a pre-charge control transistor. One or both of the clocked transistors of conventional domino logic circuits are removed, and a single clocked transistor that controls the logic state of the output of the inverter is provided. This arrangement reduces or eliminates the series resistance in line with the logic block, reduces or eliminates the capacitance contributed by the clocked pre-charge transistor of conventional domino logic circuits, and reduces the size and thus the capacitance contributed by one or more of the transistor of the inverter.</p> |
