| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to increase an operation speed of a transistor, by easily forming a graded drain, by preventing a short channel effect from being deteriorated, and by reducing overlap capacitance between a gate electrode and a source/drain. CONSTITUTION: The first gate insulation layer is formed in an active region of a silicon substrate(10), and the first gate electrode pattern is selectively formed on the first gate insulation layer. A low density ion implantation process for forming a source drain extension(SDE) portion in the silicon substrate is performed by using the first gate electrode(30) as a mask. The second gate insulation layer(50) thicker than the first gate insulation layer is formed in the silicon substrate outside the first gate electrode. The second gate electrode is formed on a sidewall of the first gate electrode. A medium density ion implantation for forming a graded drain(GD) in the silicon substrate is performed by using the first and second gate electrodes as a mask. An insulation layer spacer(70) is formed on a sidewall of the second gate electrode. A high density ion implantation for a source/drain is performed by using the first gate electrode, the second gate electrode and the spacer as a mask.
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