发明名称 PROCESSOR EQUIPPED WITH OUT-OF-ORDER EXECUTING FUNCTION
摘要 PROBLEM TO BE SOLVED: To realize the assignment of high speed rename registers in constitution in almost the same level as that of the constitution in which only one rename register is assigned even when an instruction to request the assignment of plural rename registers is present in an instruction set. SOLUTION: This processor is provided with rename register assigning mechanisms 103 and 104 for dividing a rename register 109 into plural groups, and for assigning rename registers from each group. At the time of allocating the rename registers to an instruction to store plural executed results in the same architecture register, the rename registers are allocated from the different groups to each result.
申请公布号 JP2001236222(A) 申请公布日期 2001.08.31
申请号 JP20000044077 申请日期 2000.02.22
申请人 HITACHI LTD 发明人 TANAKA KAZUNARI;KIMURA ISAO
分类号 G06F9/38;G06F9/34;(IPC1-7):G06F9/38 主分类号 G06F9/38
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