发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To eliminate the increase in the layout size by disposing an N+ type layer for supplying the well potential to an element formation region in the periphery of the element formation region planarly separating a source and drain diffusion regionm the N+ type layer by means of an element isolation insulation film, and spreading the N+ type layer like a mesh between element in the element formation region. SOLUTION: The N+ type layer 5 for supplying the well potential which is widened in the depthwise direction is formed in a semiconductor substrate at nearly the same depth where a recess 3 filled with an element isolation insulation film 4 is formed. Through holes 10 are formed in the element isolation insulation film 4 and an interlayer insulation film 9 to connect an interconnection 12 for supplying the well potential and the N+ type layer 5 through the through holes 10. As a result, the potential can be supplied to a well more efficiently and stably without increasing the layout size.
申请公布号 JP2001237396(A) 申请公布日期 2001.08.31
申请号 JP20000044873 申请日期 2000.02.22
申请人 NEC MICROSYSTEMS LTD 发明人 KUROKI KOICHI
分类号 H01L21/762;H01L21/76;H01L21/8242;H01L27/108 主分类号 H01L21/762
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