PROCESS FOR REDUCING SURFACE VARIATIONS FOR POLISHED WAFER

摘要

A process for forming a semiconductor (14) wafer whichi s single side polished improves nanotopology and flatness of the polished wafer. The process reduces the effect of back side surface features, such as edge ring phenomena and back side laser marks, on nanotopology, thereby improving oxide layer uniformity for chemical/mechanical planarization (CMP) processing, and flatness on the polished front side of the wafer after polishing block (10) by wax (12). The edge ring causes certain deformation and stress in the wafer upon mounting, which is held by the wax. After mounting, the wax is heated to allow the wafer to relax, removing the stress, without degrading the bond of the wafer to the polishing block. The wafer is polished and removed from the polishing block. The polished surface substantially retains its shape after being de-mounted from the block.