| 摘要 |
In a DRAM-logic embedded integrated circuit in which a DRAM including trench capacitors of the deep trench structure and a logic circuit are mixedly formed in a semiconductor substrate, a plurality of capacitors of the deep trench structure are provided in the logic circuit portion. The plurality of capacitors are connected in parallel by wiring portions, whereby a plurality of capacitor blocks are formed. Between the respective capacitor blocks, there are provided fuse elements which selectively connect the respective wiring portions to each other or selectively separate them from each other to thereby vary the capacitance value of the capacitance blocks. These fuse elements are selectively cut off depending on the capacitance value of the capacitors required in view of the circuit design.
|
