发明名称 INSTRUCTION RETRIEVAL AND PORT ALLOCATION (FIAP) CIRCUIT AND ITS METHOD
摘要 PROBLEM TO BE SOLVED: To provide a means to promptly and efficiently start an instruction in a non-order processor 12. SOLUTION: A means to promptly and efficiently trance down places of one or more instructions the execution of which is prepared during a launch cycle and to allocate one or more ports 22 related to one or more execution resources 23 to the instruction the execution of which is prepared during the launch cycle is provided in the non-order processor 12. The processor 12 is provided with instruction rearrangement mechanism 18 (for example, a queue) having plural slots 21 to temporarily store each of the plural instructions. The instructions are executed in non-order from the queue. Each slot 21 is provided with a FIAP circuit 10 to properly start each instruction and to prevent its start. Plural signals are continuously transmitted through the FIAP circuit 10 of the queue 18 and thus, plural defined instructions 15 corresponding to the plural defined ports 22 related to one or more execution resources 23 is started by the queue.
申请公布号 JP2001216157(A) 申请公布日期 2001.08.10
申请号 JP20010023626 申请日期 2001.01.31
申请人 HEWLETT PACKARD CO <HP> 发明人 NAFFZIGER SAMUEL D
分类号 G06F9/38;G06F9/30;(IPC1-7):G06F9/38 主分类号 G06F9/38
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