Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device

摘要

A memory cell array is divided into a plurality of banks. Each bank includes a redundant row circuit and a redundant column circuit for repairing any defective column. Data lines are separately provided to a normal memory cell array, the redundant row circuit, and the redundant column circuit. Redundancy-based column repair is performed by selectively changing connection between each data input/output line and a global data bus. Prior to the timing at which a clock signal is activated, access signals such as a command signal and an address signal are transmitted to a command decode circuit, a predecode circuit and a redundancy control circuit to perform a predecoding operation and redundancy judgement.