发明名称 Divided voltage de-coupling structure
摘要 The present invention provides an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a central node. The de-coupling circuit further includes a PMOSFET transistor and a NMOSFET transistor that have their gates coupled at the node. The PMOSFET and NMOSFET transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively.
申请公布号 US6271706(B1) 申请公布日期 2001.08.07
申请号 US19980010631 申请日期 1998.01.22
申请人 INTEL CORPORATION 发明人 NAIR RAJ
分类号 G06F1/26;(IPC1-7):H03K5/08 主分类号 G06F1/26
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