| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal processing system capable of reducing the number of external terminals and efficiently integrating circuits. SOLUTION: The system is provided with a host CPU bus interface circuit 30 for receiving an address from a host CPU 3 and inputting/outputting data to/from the CPU 3 through a bus, a write-only register group 35 and a RAM 42 for storing data inputted from the CPU 3, an interruption circuit 40 for generating an interruption signal S40 corresponding to the address inputted from the CPU 3, and a CPU 41 for conducting processing on the basis of the data stored in the RAM 42 or the like in accordance with the interruption signal S40.
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