发明名称 MICROPROCESSOR SYSTEM AND METHOD OF OPERATION
摘要 A bus (2) connects a first unit (1) to further units (3,4,5), and includes a line (21) for a status signal (BS) indicative of the operating state of the bus, and lines (22) for further bus signals (B) in the form of data. A bus control unit (11) controls the access by the first unit to the further units via the bus. If the bus control unit indicates via the status signal line (21) that no access is being made by the first unit to the further units, a data value (RNG) is randomly generated, and supplied to the lines (22) for the further bus signals (B).
申请公布号 EP1118924(A1) 申请公布日期 2001.07.25
申请号 EP20000100994 申请日期 2000.01.19
申请人 INFINEON TECHNOLOGIES AG 发明人 KNIFFLER, OLIVER
分类号 G06F13/36;G06F21/75;G06F1/00;G06F12/14;G06F21/55;G06K19/073 主分类号 G06F13/36
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