发明名称 Memory module using a vacant pin terminal for balancing parasitic capacitive loads
摘要 A memory module includes a first group of integrated-circuit memory units each having a control pin terminal, and a second group of integrated-circuit memory units. Each memory unit of the second group includes a control pin terminal and at least one memory unit of the second group further includes at least one vacant pin terminal. First connections are provided for receiving a control signal from an external source and supplying it to the control pin terminal of each of the first group of memory units. Second connections are provided for receiving and supplying the control signal to the control pin terminal of each of the second group of memory units and to at least one vacant pin terminal of the second group of memory units. Preferably, the vacant pin terminal is connected to a circuit equivalent in operating characteristics to a circuit connected to the control pin terminal.
申请公布号 US6266265(B1) 申请公布日期 2001.07.24
申请号 US20000572661 申请日期 2000.05.16
申请人 NEC CORPORATION 发明人 SAKURAGI SHINJI
分类号 G11C11/401;G11C5/06;H01L23/50;H01L25/10;H01L25/18;H01L27/10;(IPC1-7):G11C5/06 主分类号 G11C11/401
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