| 摘要 |
PURPOSE: A method for forming a metal gate using a damascene structure is provided to obviate a problem that a gate electrode of low resistance can not be formed using a poly as a design rule of the gate electrode decreases. CONSTITUTION: The second conductive layer and the sixth dielectric layer(29) are selectively removed by using a CMP process so as for a surface of an interlayer dielectric to be exposed. A metal gate electrode(30a) is formed in this manner. The interlayer dielectric is removed by using a wet etching process. The wet etching process is performed in a chemical mixing SC1 and HF. When the interlayer dielectric is removed, a metal gate electrode(30a), the third dielectric sidewall(25) and the first dielectric layer(22) which is formed within a trench are protected by the fourth and fifth dielectric layers. The fifth dielectric layer is removed by using a dry etching process. After the fourth dielectric layer is removed by using a wet etching process, a silicide layer(31) is formed on a source/drain region by using a silicide process. Since an active region becomes silicide, a low resistance of the gate electrode and a low resistance of the source/drain can be simultaneously realized.
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