| 摘要 |
PURPOSE: A counting circuit for a data pre-fetch is provided to enough secure the margin of a data access time even in operating a semiconductor memory device at high speed. CONSTITUTION: The counting circuit includes a pass gate signal generating portion(10), first through third latching portions(110,130,150) and first through third pre-fetch signal generating portions(120,140,160). The pass gate signal generating portion generates a pass gate signal by logically mixing a read line signal and a read signal. The first through third latching portions are synchronized with the pass gate signal and respectively latch a signal generated from a former terminal of the first through third pre-fetch signals. The first pre-fetch signal generating portion generates the first pre-fetch signal by logically mixing the read signal and an outputting signal of the first latching portion. The second pre-fetch signal generating portion generates the second pre-fetch signal by logically mixing the read signal, the delayed signal and an outputting signal of the second latching portion. The third pre-fetch signal generating portion generates the third pre-fetch signal by logically mixing the read signal, the delayed signal and an outputting signal of the third latching portion.
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