SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN DEVICE AND LAYOUT CELL GENERATION METHOD

摘要

PROBLEM TO BE SOLVED: To solve such a problem that unnecessary power consumption is caused since a pin not inputted to any circuits and an inverter circuit for driving only the pin are present among the pins outputting from a flip-flop and a latch circuit in layout data generated by conventional circuit design. SOLUTION: The layout data designed through logic synthesis and the layout of cells and a net list for which the description of an excessive circuit part driving only an unconnected pin or the like is eliminated from the net list required for generating the layout data are generated. By LVS-verifying the two, an LVS error is generated and the excessive circuit of a part where the error is generated is eliminated or gate-fixed.