| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which DQS glidge resistance is improved and which has DDR constitution being easy to use. SOLUTION: This device is a dynamic RAM of which operation of an internal circuit is controlled synchronizing with a clock signal, the device is provided with an input circuit in which plural write-in data inputted in serial corresponding it are taken successively in plural first latch circuits by using a second clock signal inputted at the time of write-in operation, write-in data taken in the first latch circuit is taken in the second latch circuit by using the first clock signal and it is transmitted to an input/output data bus, the third clock signal is formed by providing a logic circuit masking a noise generated at the time of finish of the second clock signal by logic of the first clock and the second clock signals, and it is supplied to the first latch circuit outputting the write-in data to an input of the second latch circuit. |
