| 摘要 |
PURPOSE: A method of reducing undesired etching of insulation due to elevated boron concentrations is provided to substantially eliminate such boron-rich zones in the insulation layers, and reduce defective etching of these layers and the electrical short-circuits resulting therefrom. CONSTITUTION: A semiconductor wafer(10) has a substrate(12) with a surface(12A). Field effect transistors(14, 16) are formed in substrate(12) and on surface(12A). Transistor(14) comprises a drain region(18) and a source region(20) which are separated by a portion of substrate(12). Located on surface(12A) is a gate dielectric layer(26) which is above and covers the portion of substrate(12A) which separates drain region(18) from source region(20). A conductive gate layer(28) covers gate dielectric layer(26). Conductive layer(28) can be doped poly-silicon or metal. The transistor(16) is essentially identical to transistor(14) and comprises drain region(22), source region(24), a gate dielectric layer(30), and a conductive gate layer(32). Source region(20) of the transistor(14) is separated from the transistor(16) by a portion of substrate(12) and optionally by a dielectric region(25) formed in the portion of substrate(12) between the transistors(14 and 16). The transistors(14, 16) and surface(12A) is an insulating layer(34), which has a top surface(34A).
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