| 摘要 |
PURPOSE: A switching circuit of clock signal is provided to prevent the mal-functioning of the system by eliminating glitch during the switching to another clock signal. CONSTITUTION: In the switching circuit of clock signal, a delay clock control unit(41) delays a clock enable signal(enable_clk_a) sequentially using a clock signal(clk_a) and generates a clock control signal(go_clk_a) by conducting an AND logic with the delayed signals. Another delay clock control unit(42) delays a clock enable signal(enable_clk_b) sequentially using a clock signal(clk_b) and generates a clock control signal(go_clk_b) by conducting an AND logic with the delayed signals. An AND gate(AD41) produces the clock signal A(clk_a) as the current clock signal(current_clk_a) responding to the clock control signal A(go_clk_a). Another AND gate(AD42) produces the clock signal B(clk_b) as the current clock signal(current_clk_b) responding to the clock control signal B(go_clk_b). An OR gate(OR41) produces the final output clock signal(clock_out) by conducting an OR logic with the two current clock signals(current_clk_a,current_clk_b).
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