发明名称 INTERFACE BETWEEN CPU AND DSP IN CDMA MOBILE COMMUNICATION SYSTEM
摘要 PURPOSE: An interface device between a CPU(Central Process Unit) and a DSP(Digital Signal Processor) in a CDMA(Code Division Multiple Access) mobile communication system is provided to automatically switch a mode of a CPU to a stand-by mode in case a transmitting register mode is an empty mode or voice data are written in receiving registers of several DSPs. CONSTITUTION: In the device having a number of DSPs(Digital Signal Processor)(200) and a decoder(400), a waiting signal controller(500) is furthermore included. In the controller, the signal input terminals of the device are individually connected to the input buffer full pins(Pibf) and output buffer empty pin(Pobe) of a number of DSPs while their output terminals are connected to the awaiting signal input terminal(Wait) of a CPU(Central Process Unit)(100), so that the connection to a random DSP among a number of DSPs is decided by chip select signal output from a decoder. Thereafter, if voice data are written in the corresponding DSP receiving register(201) or the transmitting register(202) is empty, a high signal is output from the input buffer full pin or the output buffer empty pin and a low signal and the waiting signal are output to CPU in order to switch a mode of the CPU into stand-by mode. If all of the input buffer full pin and the output buffer empty pin output low signals as the corresponding DSP receiving register is empty and transmitting register is not empty, a high signal and an active signal is output to the CPU in order to switch a mode of the CPU into active mode.
申请公布号 KR20010056947(A) 申请公布日期 2001.07.04
申请号 KR19990058644 申请日期 1999.12.17
申请人 HYNIX SEMICONDUCTOR INC. 发明人 YUM, YUN JONG
分类号 H04B1/40;(IPC1-7):H04B1/40 主分类号 H04B1/40
代理机构 代理人
主权项
地址