| 摘要 |
PROBLEM TO BE SOLVED: To obtain a digital synchronous circuit capable of outputting an output clock signal OUTCLK having no hazard in the case of selecting one among a plurality of clock signals CLK1 to CLKn synchronizing with an input data signal DIN. SOLUTION: This digital synchronous circuit includes a clock generation circuit 10 outputting the plurality of clock signals CLK1 to CLKn in which frequencies are the same and phases are different from one another, a selection signal 60 outputting a clock signal selected by a selection signal SL, while a corresponding clock signal is given to each data input port and the selection signal SL is given to a control input port, and a selection control circuit 70 outputting the selection signal SL in accordance with a clock selection signal CSL and the plurality of clock signals CLK1 to CLKn. Timing when a value shown by the selection signal SL of the circuit 70 is changed from a 1st value to a 2nd value is made to be any of periods when the potential level of a clock signal shown at the 1st value and the potential level of the clock signal shown at the 2nd value coincide with each other. |
